W. Lu ; P. O'Connor ; J. Fried and J. Kuczewski " CCD emulator design for LSST camera ", Proc. SPIE 9915, High Energy, Optical, and Infrared Detectors for Astronomy VII, 99152O (July 27, 2016); doi:10.1117/12.2234033; http://dx.doi.org/10.1117/12.2234033
Publication Date:
Wednesday, July 27, 2016
Type:
Conference Papers
SPIE
Citable:
no
SPIE Proceedings
Volume:
9915
Abstract:
As part of the LSST project, a comprehensive CCD emulator that operates three CCDs simultaneously has been developed for testing multichannel readout electronics. Based on an Altera Cyclone V FPGA for timing and control, the emulator generates 48 channels of simulated video waveform in response to appropriate sequencing of parallel and serial clocks. Two 256Mb serial memory chips are adopted for storage of arbitrary grayscale images. The arbitrary image or fixed pattern image can be generated from the emulator in triple as three real CCDs perform, for qualifying and testing the LSST 3-stripe Science Raft Electronics Board (REB) simultaneously. Using the method of comparator threshold scanning, all 24 parallel clocks and 24 serial clocks from the REB are qualified for sequence, duration and level before the video signal is generated. In addition, 66 channels of input bias and voltages are sampled through the multi-channel ADC to verify that correct values are applied to the CCD. In addition, either a Gigabit Ethernet connector or USB bus can be used to control and read back from the emulator board. A user-friendly PC software package has been developed for controlling and communicating with the emulator. © (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Reviewed Under:
LSST Project Publication Policy
Bibtex reference:
@proceeding{doi:10.1117/12.2234033,
author = {Lu, W. and O'Connor, P. and Fried, J. and Kuczewski, J.},
title = {
CCD emulator design for LSST camera
},
journal = {Proc. SPIE},
volume = {9915},
number = {},
pages = {99152O-99152O-8},
abstract = {
As part of the LSST project, a comprehensive CCD emulator that operates three CCDs simultaneously has been developed for testing multichannel readout electronics. Based on an Altera Cyclone V FPGA for timing and control, the emulator generates 48 channels of simulated video waveform in response to appropriate sequencing of parallel and serial clocks. Two 256Mb serial memory chips are adopted for storage of arbitrary grayscale images. The arbitrary image or fixed pattern image can be generated from the emulator in triple as three real CCDs perform, for qualifying and testing the LSST 3-stripe Science Raft Electronics Board (REB) simultaneously. Using the method of comparator threshold scanning, all 24 parallel clocks and 24 serial clocks from the REB are qualified for sequence, duration and level before the video signal is generated. In addition, 66 channels of input bias and voltages are sampled through the multi-channel ADC to verify that correct values are applied to the CCD. In addition, either a Gigabit Ethernet connector or USB bus can be used to control and read back from the emulator board. A user-friendly PC software package has been developed for controlling and communicating with the emulator.
},
year = {2016},
doi = {10.1117/12.2234033},
URL = { http://dx.doi.org/10.1117/12.2234033},
eprint = {}
}